In multi-core processors, scanning of circuit logic (e.g., integrated circuit logic) is an important structural design process, supporting a number of functions such as power-on-reset sequencing, data bring-up, error debugging, and recovery. One characteristic of existing scan verification techniques is that they fail to detect corruption in a non-scanned portion of logic, where that corruption is due to a corrupt fence or an architectural bug.
Logic scanning is traditionally used by verification engineers as a last resort (in the design phase) for debugging failures. One of the expectations placed on the scanning process is to identify debugging failures by scanning out a minimum amount of logic without corrupting non-scanned logic. However, it is difficult to design control logic capable of partitioning the circuit into manageable (minimal) pieces using fences/partitions, where the amount of logic in these chip designs continues to increase. In turn, verification engineers face a difficult task of ensuring that each non-scanned piece of logic retains its data after scanning.